ADSP-214xx SHARC Processor Hardware Reference I-31
Index
TWI controller bits (continued)
clock high (TWICLKHI), A-116,
A-117, A-254
clock low (TWICLKLOW), A-115,
A-116, A-254
data not acknowledged (TWIDNAK),
A-261
data transfer count (TWIDCNT), A-259
enable (TWIEN), A-254
fast mode (TWIFAST), A-258
general call enable (TWIGCE), A-256
issue stop condition (TWISTOP), A-259
lost arbitration (TWILOST), A-261
master address length (TWIMLEN),
A-258
master mode enable (TWIMEN), A-258
master transfer direction (TWIMDIR),
A-258
master transfer in progress
(TWIMPROG), A-261
not acknowledged (TWINAK), A-256
repeat START (TWIRSTART), A-259
serial clock override (TWISCLOVR),
A-259
serial clock sense (TWISCLSEN), A-262
serial data override (TWISDAOVR),
A-259
serial data sense (TWISDASEN), A-262
slave address length (TWISLEN), A-255
slave enable (TWISEN), A-255
slave transmit data valid (TWIDVAL),
A-255
TWI controller registers
clock divider (TWIDIV), A-254
RXTWI16 (16-bit receive FIFO)
register, 21-14
RXTWI8 (8-bit receive FIFO), 21-13
TWIMADDR (master mode address),
A-260
TWI controller registers (continued)
TWIMCTL (master mode control),
A-257
TWIMSTAT (master mode status),
A-260
TWISADDR (slave mode address),
A-256
TWISCTL (slave mode control), A-255
TWISSTAT (slave mode status), A-256
TXTWI16 (16-bit transmit FIFO),
21-12
TXTWI8 (8-bit transmit FIFO), 21-12
two channel mode (S/PDIF), 13-12
TXFLSH (flush transmit buffer) bit, 15-35,
A-236
TXS_A (data buffer channel B status) bit,
A-158, A-161, A-166
TXSPI, TXSPIB (SPI transmit buffer)
registers, A-239
TXSPI (SPI transmit buffer) register, 2-10,
15-20,
15-30
TXSP
x (serial port transmit buffer)
registers, 2-10
TXSR (SPI transmit shift) register, 15-8
TX_UACEN (DMA transmit buffer
enable) bit, 20-5
U
UART, 20-1
baud rate, 20-10, 20-11
baud rate examples, 20-5
bock diagram, 20-7
chained DMA, 2-15, 20-14
core transfers, 20-12
data ready flag, 20-12
data word, 20-10
divisor, 20-4, A-249
divisor reset, 20-5
DMA transfers, 20-13
sampling clock period, 20-12
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