Clocking
15-6 ADSP-214xx SHARC Processor Hardware Reference
SPI Control (SPICTLx). This register configures the fundamental trans-
fer initiation mode (core or DMA) and configure timing bits and enable
the SPI port.
SPI DMA Control (SPIDMACx). This register control the DMA channel
on SPI and corresponding status bits provide status or error information
on transmission.
SPI Flag (SPIFLAGx). This control register enables the chip selects out-
put in master mode and returns status for errors in multiprocessor
systems.
SPI Status (SPISTATx). This status register provide information on trans-
mission errors for the core.
SPI Baud rate (SPIBAUDx). For master devices, the clock rate is deter-
mined by the 15-bit value of the baud rate registers (
SPIBAUDx) as shown
in Table 15-4. For slave devices, the value in the SPIBAUDx register is
ignored.
Clocking
The fundamental timing clock of the SPI module is peripheral clock/4
(PCLK/4) for slave mode and peripheral clock/8 (PCLK/8) for master mode.
In master mode the settings define the SPI master clock. The baud rate,
ssettings are shown in Table 15-4.
Table 15-4. SPI BAUD Rate – PCLK = 200 MHz
BAUDR Bit Setting Divider SPICLK
0N/AN/A
1N/AN/A
2825
3 12 16.66
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