External Port DMA
3-112 ADSP-214xx SHARC Processor Hardware Reference
single reads from each TAP are shown for simplicity and block reads are
default, depending on the count specified in the
RCEP register.
1. Writes to external memory. The number of writes is determined by
the ICEP register. The data is fetched from the IIEP register and the
IMEP register is used as the internal modifier. The EIEP register
serves as the external index and is incremented by the EMEP register
after each write. These writes are circular buffered if circular buff-
ering is enabled.
2. In chained DMA, when the writes are complete, (ICEP = zero) the
EIEP register, which serves as the write pointer of the delay line, is
written back to the internal memory location from where it was
fetched.
3. Reads from external memories. For reads, the tap list (TL) modifi-
ers are used and the number of reads is determined by the RCEP
register. The write pointer in the EIEP register serves as the index
address for these reads (reads start from where writes end). The
EIEP register, along with tap list modifiers, are used in a pre-modify
addressing mode to create the external address for the writes.
Therefore, for each read, the DMA controller fetches the external
modifier from the tap list and the reads are circular buffered (if
enabled).
External Address Calculation for Reads
Note that TL[N] is the first tap list entry in internal memory pointed to
by the tap list pointer register (
TPEP). Tap list entries are 27-bit signed
integers. Therefore, for each read-block, the DMA state machine fetches
the offset external modifier from the tap list. The reads are circular buff-
ered if circular buffering is enabled.
The external address generation follows pre-modify addressing for
reads in delay line DMA and therefore the
EIEP register values are
not modified. Also the
EMEP register does not have any effect during
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