ADSP-214xx SHARC Processor Hardware Reference A-175
Registers Reference
Input Data Port Control Register 0 (IDP_CTL0)
Use this register to configure and enable the IDP and each of its channels.
The register is shown in Figure A-93 and described in Table A-90.
Figure A-93. IDP_CTL0 Register
IDP_SMODE7 (31–29)
Buffer Hang Disable
IDP_SMODE6 (28–26)
IDP_SMODE3 (19–17)
IDP_SMODE4 (22–20)
IDP_SMODE5 (25–23)
IDP_SMODE2 (16–14)
IDP_SMODE1 (13–11)
IDP_EN
IDP_NSET (3–0)
IDP_BHD
IDP_DMA_EN
IDP_CLROVER
Channel 7 Serial Mode Select
Channel 6 Serial Mode Select
Channel 3 Serial Mode Select
Channel 4 Serial Mode Select
Channel 5 Serial Mode Select
Channel 2 Serial Mode Select
Channel 1 Serial Mode Select
Global IDP Enable
Number of FIFO entries
IDP_SMODE0 (10–8)
Channel 0 Serial Mode Select
Global IDP DMA Enable
Clear FIFO Overflow
IDP_SMODE2 (16–14)
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
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