Effect Latency
4-22 ADSP-214xx SHARC Processor Hardware Reference
Buffer Hang Disable (BHD)
A buffer hang disable (BHD) bit has been provided in the control register
(LPCTLx). Setting this bit to 1 prevents the core from hanging when a read
from an empty receive buffer or a write to a full transmit buffer is
attempted. If the BHD bit is set and a read is performed from an empty
receive buffer, then the previous data is returned. Writing to a full trans-
mit buffer with the BHD bit set overwrites the existing data.
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
Link Port Effect Latency
After the link port registers are configured the effect latency is 2 PCLK
cycles.
Programming Model
The following sections provide information on programming receive and
transmit DMA and changing the link port clock.
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