ADSP-214xx SHARC Processor Hardware Reference 10-57
Serial Ports
3. Write the start address of the first TCB of the new chain into the
chain pointer register.
4. Resume chained DMA mode by setting
SDENx = 1 and SCHENx = 1.
Setting Up and Starting Multichannel Mode
Use the SPCTLx and channel selection registers (SPMCTLx) to configure the
serial ports to run in multichannel mode as follows. For proper data align-
ment on sports in multichannel mode, the multichannel enable bit must
be set last.
1. Clear all control registers (SPCTLx/y and SPMTCLxy)
2. Configure the channel section registers (SPxCSx and SPyCSx).
3. For DMA mode operation, configure the DMA parameter registers
(Index, Modify and Count). For DMA chaining, initialize the
chain pointer register with the index register for the first chain.
4. Configure the transmitter SPORTx control register of a SPORTxy
pair (SPCTLx) and enable the DMA/DMA chaining.
5. Configure the receiver SPORTy control register of pair SPORTxy
pair (SPCTLy) and enable the DMA/DMA chaining.
6. In multichannel and packed I
2
S modes, the frame sync is indepen-
dent of data. In multichannel/packed I
2
S mode, operation starts as
soon as the MCEx bit is enabled.
Due to the priority of other DMA channels, if the DMA controller
does not load the transmit buffer with the actual value from mem-
ory, then the older value is transmitted out. Therefore, for
DMA/DMA chaining mode, wait for the transmit buffer status to
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