Programming Model
16-22 ADSP-214xx SHARC Processor Hardware Reference
3. Set the
TIMEN bit. The timer performs boundary exception checks
on the period and width values:
• If (width == 0 or Period < width or period == width) both
the OVF_ERR and IRQ bits are set.
• If there are no exceptions, the width value is loaded into the
counter and it starts counting.
The timer produces PWM waveform with a period of 2 x period
and a width of 2 x width.
• When 2 x width expires, the counter is loaded with
2x(period – width) and continues counting.
• When 2 x period expires, the counter is loaded with 2 x
width value again and the cycle repeats.
• When the width or period expires, the IRQ bit (if enabled) is
set depending on the PRDCNT bit.
• When IRQ is sensed, read the status register (TMxSTAT) and
perform the appropriate “write-one” to clear.
WDTH_CAP Mode
Use the following procedure to configure and run the timer in
WDTH_CAP out mode.
1. Reset the
TIMEN bit and set the configuration mode to 10 to select
WDTH_CAP operation. This configures the
TIMERx_I pin as an
input pin with its polarity determined by the PULSE bit.
• The timer measures a positive active pulse width at the
TIMERx_I pin.
• The timer measures a negative active pulse width at the
TIMERx_I pin.
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