Peripheral Registers
A-74 ADSP-214xx SHARC Processor Hardware Reference
Duty Cycle Low Side Registers (PWMALx, PWMBLx)
The 16-bit duty-cycle control registers (RW) directly control the AL/BL
duty cycles (two’s-complement) of the non-paired PWM signals. These
can be different from the AH/BH cycles.
Dead Time Registers (PWMDTx)
These 16-bit RW registers set up a short time delay (10-bit, unsigned)
between turning off one PWM signal and turning on its complementary
signal.
Debug Status Registers (PWMDBGx)
These 16-bit registers aid in software debug activities.
FFT Accelerator Registers
The following sections describe the registers used to program and debug
the FFT accelerator.
Table A-41. PWMDBGx Register Bit Descriptions (RO)
Bit Name Function
0 PWM_AL Channel A Low Output Signal for S/W Observation
1 PWM_AH Channel A High Output Signal for S/W Observation
2 PWM_BL Channel B Low Output Signal for S/W Observation
3 PWM_BH Channel B High Output Signal for S/W Observation
15:4 Reserved
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