ADSP-214xx SHARC Processor Hardware Reference 2-45
I/O Processor
is in group A), SP1 has the highest priority. Programs can change DMA
arbitration modes between fixed and rotate on the fly which incurs an
effect latency of 2
PCLK cycles.
Interrupts
The primary type of DMA communication is interrupt driven I/O where
the core continues to execute instructions while DMA executes in the
background. This allows high levels of parallelism achieving over all better
system performance. Because the interrupt vector directs the core to
respond to specific transactions very efficiently, programs do not need to
poll status bits.
During interrupt-driven DMA, programs use the interrupt mask bits in
the IMASK, LIRPTL, DPI_IMASK, DAI_IMASK_x registers to selectively mask
DMA channel interrupts that the I/O processor latches into the IRPTL,
LIRPTL, DPI_IMASK, DAI_IMASK_x registers. A channel interrupt mask in the
IMASK, LIRPTL, DPI_IMASK, DAI_IMASK_x registers determines whether a
latched interrupt is serviced or not. When an interrupt is masked, it is
latched but not serviced.
Sources
The following sections describe the two sources of interrupts.
Unchained DMA Interrupts
When an unchained (single block) DMA process reaches completion (the
DMA count decrements to zero) on any DMA channel, the I/O processor
latches that DMA channel’s interrupt. It does this by setting the DMA
channel’s interrupt latch bit in the IRPTL, LIRPTL, DPI_IMASK, or
DAI_IMASK_x registers.
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