Interrupts
4-18 ADSP-214xx SHARC Processor Hardware Reference
corresponding status register (
LSTATx). Reading the status register clears
the interrupt bits. Read of the status register when an interrupt occurs
causes the core to hang till the interrupt bits are set in the status register.
Otherwise simultaneous read of the status register and updating of the sta-
tus register will result in loss of information. This hang cannot be
overridden with the BHD bit LPCTLx register.
Access Completion
An external transfer complete interrupt is generated by the transmitter
once the external transfer is completed by setting bit 12
(EXTTXFR_DONE_MSK) in the LCTL register. When DMA is not enabled, this
interrupt is generated when the transmitter FIFO is empty and the last
byte has been transmitted. Also, when DMA is enabled, the DMA engine
checks if DMA has been completed. (If CLBx is zero, and chaining is
enabled, the DMA engine also checks if CPLBx also is zero.)
Internal Transfer Completion
This interrupt performs like previous SHARC processors where an inter-
nal transfer complete interrupt is generated by the transmitter once the
word count is zero by setting bit 10 (DMACH_IRPT_MSK) in the LCTL register.
When DMA is not enabled, this interrupt is generated when the word
count is zero. Also, when DMA is enabled, the DMA engine checks if
DMA has been completed. (If
CLBx is zero, and chaining is enabled, the
DMA engine also checks if
CPLBx also is zero.)
For correct operation, programs should not perform simultaneous
reads and updates of the status register as this results in loss of
information. When an interrupt occurs, reads of the status register
cause the core to hang until the interrupt bits are set in the status
register. This hang cannot be overridden with the
LP_BHD bit in the
LCTLx register.
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