Debug Features
9-40 ADSP-214xx SHARC Processor Hardware Reference
registers provide a way to specify which interrupts to notice and handle,
and which interrupts to ignore. These dual registers function like
IMASK
does, but with a higher degree of granularity.
The DAI/DPI interrupt controller has the same interrupt latency
like the core interrupt controller which takes 6 cycle latency to
respond to asynchronous interrupts.
Note that IRPTL and LIRPTL are system registers. All DAI interrupt regis-
ters (DAI_IMASK_x) are memory mapped registers.
Debug Features
The following sections describe features that can be used to help in debug-
ging the DAI.
DAI Shadow Registers
The DAI_IMASK_L_SH and DAI_IMASK_H_SH shadow registers are provided
for the DAI_IMASK_L and DAI_IMASK_H registers respectively. Reads of these
registers returns data in DAI_IMASK_L and DAI_IMASK_H respectively with-
out clearing the contents of these registers.
DPI Shadow Registers
The DPI_IMASK_SH shadow register is provided for register DPI_IMASK. A
read of this register (RO) returns data in DPI_IMASK without clearing the
contents of this register.
Loop Back Routing
The serial peripherals (SPORT and SPI) support an internal loop back
mode. If the loop back bit for each peripheral is enabled, it connects the
transmitter with the receiver block internally (does not signal off-chip).
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