ADSP-214xx SHARC Processor Hardware Reference 15-35
Serial Peripheral Interface Ports
With enabled SPI:
1. Poll the
SPIFE bit in the SPISTAT register. If this bit is high the SPI
buffer can be cleared.
2. Clear the RXSPIx/TXSPIx buffers and the buffer status without dis-
abling the SPI. This can be done by ORing 0xC0000 with the
present value in the SPICTLx register. For example, programs can
use the RXFLSH and TXFLSH bits to clear TXSPIx/RXSPIx and the buf-
fer status.
3. Clear the SPIDMAC register.
4. Clear all errors by writing to the W1C-type bits in the SPISTAT reg-
ister. This ensures that no interrupts occur due to errors from a
previous DMA operation.
5. Reconfigure the SPICTL register to remove the clear condition on
the TXSPI/RXSPI registers.
6. Configure DMA by writing to the DMA parameter registers and
the SPIDMACx registers using the SPIDEN bit (bit 0).
Switching From Receive to a New DMA
Use the following sequence to switch from receive to transmit DMA. Note
that TXSPIx and RXSPIx are registers but they may not contain any bits,
only address information.
With disabled SPI:
1. Poll the SPIFE bit in the SPISTAT register. If this bit =1 the SPI can
be disabled.
2. Clear the SPICTLx registers to disable the SPI. Disabling the SPI
also clears the
RXSPIx/TXSPIx register contents and the buffer
status.
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