ADSP-214xx SHARC Processor Hardware Reference A-169
Registers Reference
SPORT Multichannel Control Registers (SPMCTLx)
The serial ports in the ADSP-214xx processors work individually, not in
pairs. Therefore, each SPORT has its own multichannel control register.
These registers are shown in Figure A-90 and described in Table A-88.
Note that in ADSP-2136x SHARC processors there is one
SPMCTLxy regis-
ter for each TDM pair, so its enough to write into one register, for both
SPORTs.
On the ADSP-214xx SHARC processors, each sport has its own
SPMCTLx register, so only one write into both SPMCTLx registers is required
to operate the SPORTs as pairs. Since there is no change in SPMCTLx regis-
ter bit definitions, the same value can be written into both SPMCTLx
registers in order to make legacy programs for the ADSP-2136x processors
operate correctly.
Figure A-90. SPMCTLx Registers – Multichannel Mode
DMACHSxB
SPORTx Channel B Status
DMA Chaining Status
CHNL (22–16)
Current Channel Status
DMASxA
SPORTx Channel A DMA
Status
MCEB
Multichannel Enable
B Channels
DMACHSxA
SPORTx Channel A Status
DMA Chaining Status
DMACHSyB
SPORTx Channel B Status
DMA Chaining Status
DMACHSyA
SPORTx Channel A Status
DMA Chaining Status
DMASyB
SPORTx Channel B
DMA Status
DMASyA
SPORTx Channel A DMA
Status
DMASxB
SPORTx Channel B DMA
Status
SPL
MCEA
Multichannel Enable
A Channels
MFDx (4–1)
Multichannel Frame Delay
SPORT Loopback
NCH (11–5)
Number of Channels – 1
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
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