Index
I-10 ADSP-214xx SHARC Processor Hardware Reference
external port DMA direction change, 2-23
external port registers, A-45 to A-63
AMI control (AMICTLx), A-21, A-47
control (EPCTL), 3-130
F
FE, format extension, See SPORTs, word
length
FFT accelerator, 6-3 to 6-20
block diagram, 6-6
chained DMA, 2-18
chain pointer register (FFTICP), 6-16
circular buffer addressing, 6-17
circular buffer chained DMA, 6-15
compute block, 6-5
data transfer types, 6-15
debug feature and strategy description,
6-20, 6-65
debugging, 6-27, 6-52
enable (ENABLE) bit, 6-7
horizontal, 6-13
H point coefficient buffer, 6-9
idle state, 6-7
interrupts, 6-18
interrupts, setting, 6-18
interrupt sources, DMA, 6-18
inverse, 6-15
large, 6-26
large, computation, 6-11
memory, coefficients, 6-6
memory, data, 6-6
memory, twiddle coefficients, 6-6
packed and unpacked date, 6-8
packing bits (FFT_CPACKIN,
FFT_CPACKOUT), 6-14
processing state, 6-7
programming, 6-26
read state, 6-7
registers, 6-5
repeat (FFT_RPT) bit, 6-7
FFT accelerator (continued)
repeat mode, 6-14
reset (FFT_RST) bit, 6-7
reset state, 6-7
small, computation, 6-11
special coefficient buffer, 6-10
special product, 6-12
start (START) bit, 6-7
storing small FFTs, 6-8
TCB structure, 6-18
vertical FFT example, 6-12
V point coefficient buffer, 6-9
write state, 6-7
FFT bits
interrupt (ACC_INT0, ACC_INT1),
6-18
FIFO
see also bu
ffer
data packing in IDP, 11-18
IDP, 11-6
IDP modes use, 11-11
receive, SPORT, 10-16
SPI, 15-9
SPI DMA, 15-22
to memory data transfer, 11-14
transmit, SPORT, 10-40
FIG, frame ignore, See SPORTs, framed
and unframed data
FIR
channel control register (FIRCTL2),
A-82
control register 1 (FIRCTL1), A-80
DMA status register (FIRDMASTAT),
A-85
MAC status register (FIRMACSTAT),
A-83
FIR accelerator, 6-28 to 6-54
block diagram, 6-30
buffer, data, 6-33
chained DMA, 2-16
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