Analog Devices SHARC ADSP-214 Series - Page 1169

ADSP-214xx SHARC Processor Hardware Reference I-11
Index
FIR accelerator (continued)
coefficient memory, 6-32
debug, 6-45
decimation, 6-38
delay line (TAP), 6-32
DMA transfers, 6-42
FIR_UPSAMP bit, 6-39
formats, fixed-point, 6-42
formats, floating-point, 6-42
input sample, 6-33
interpolation, 6-39
interrupt sources, 6-45, 6-65
MAC unit, 6-31, 6-32
multiply accumulators, 6-32
pre-fetch data, 6-33
registers, 6-28, 6-32
sample ratio (FIR_RATIO) bit, 6-39
single rate operations, 6-38
TAP delay line, 6-33
window size (WINDOW) bit, 6-39
FIR bits
channel auto iterate (FIR_CAI), A-80
channel complete interrupt
(FIR_CCINTR), A-81
channel number select (FIR_CH32–1),
A-80
DMA enable (FIR_DMAEN), A-80
rounding mode select (FIR_RND), A-81
tap length (TAPLEN), A-82
window size (WINDOW), A-82
FIR filter inner loop, 3-97
flags
flag interrupt mode (IRQxEN) bits, A-5
input/output (FLAGx) pins, 10-12, 15-9
restriction with SPI bits, 7-4
SPORT pins, 10-12
FLAGx pins, 10-12, 15-9
floating-point, 1-1
40-bit, IIR, 6-61
FIR data format, 6-42
floating-point (continued)
FIR multiplier, 6-31
format select bit, IIR (IIR_FORTYBIT),
A-89
IIR accelerator, 6-59
multipliers and adders, FFT, 6-5
overflow, 6-18
radix-2 complex FFT, 6-3
rounding bit, FIR (FIR_RND), A-81
force load mode register command, 3-
52
framed versus unframed data, 10-26
frame sync
A source (FSASOURCE) bit, A-193
early vs. late, 10-27
frequencies, 10-8
in multichannel mode, 10-32
internal vs. external, 10-18
output, synchronizing, 14-21
PCG B source (FSBSOURCE) bit,
14-13
rates, setting, 10-29
routing control (SRU_FS0) registers
(group C), A-128
signals, configuring, 10-11
frame sync delay (MFD), 10-33
frame sync required (FSR) bit, A-155
framing bits, 10-29, 10-31
FRFS (frame on rising frame sync) bit,
10-29, 10-31
FS_BOTH (frame sync both) bit, A-156
FSM, frame synchronization mode, See
SPORTs, framed and unframed data
FSP, frame synchronization polarity, See
SPORTs, framed and unframed data
FSR (frame sync required) bit, A-155
full-duplex operation, specifications, 10-11
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