Index
I-22 ADSP-214xx SHARC Processor Hardware Reference
S
sample/window based processing mode,
IIR, 6-38, 6-61
sampling clock period, UART, 20-12
sampling point, UART, 20-11
saving power, 22-6, 22-12
SCHEN_A and SCHEN_B (serial port
chaining enable) bit, A-156, A-160,
A-164
SDEN (serial port DMA enable) bit,
A-156, A-160, A-164
SDRAM, 3-36, 3-73
bus errors, 3-44, 3-80
clock equation, 3-33
core address mapping, 3-27
multibank operation, 3-35, 3-71
refresh rate, 3-33
refresh rate control register (SDRRC),
A-58
registers, A-51 to A-59
restrictions, 3-27
status register (SDSTAT), A-55
SDRAM bits
CAS latency (SDCL), A-53
column address width (SDCAW), A-54
disable clock and control (DSDCTL),
A-53
external data path width (X16DE), A-54
force auto refresh (Force AR), A-54
force load mode register write (Force
LMR), A-55
force precharge (Force PC), A-54
optional refresh (SDORF), A-54
page size is 128 words (PGSZ 128), A-55
pipeline option with external register
buffer (SDBUF), A-55
power-up mode (SDPM), A-53
power-up sequence start (SDPSS), A-54
RAS setting (SDTRAS), A-53
RDC setting (SDTRCD), A-55
refresh delay (RDIV), A-59
row address width (SDRAW), A-55
RP setting (SDTRP), A-53
self-refresh enable (SDSRF), A-54
WR setting (SDTWR), A-54
SDRAM controller, 3-17
addressing (16-bit), 3-28 to 3-30
calculating refresh rate, 3-3
3
clock frequencies, 3-6
external memory access timing, 3-5
power-up sequence, A-54, A-55
read/write command, 3-22
refresh rate (SDRRC) register, 3-32
setting bank column address width, A-55
write before precharge (SDTWR) bit,
3-5
SDRAM controller commands
auto-refresh, 3-24
bank activate, 3-21
command pin states, 3-25
load mode register, 3-21
NOP/command inhibit, 3-24
precharge all, 3-22
self-refresh, 3-44, 3-79
single precharge, 3-21
SENDZ (send zeros) bit, A-233
serial clock (SPORTx_CLK) pins, 10-11
serial communications, 20-7
serial inputs, 11-6
serial peripheral interface, See SPI
setting up DMA on SPORT channels,
10-46
setup time, inputs, 23-36
shared memory
see also external port
shift register, 2-27
short word data, I/O processor, 2-27
signal routing unit external miscellaneous
(MISCAx) registers, 14-13
signal routing unit See SRU, DAI
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