DDR2 DRAM Controller (ADSP-2146x)
3-80 ADSP-214xx SHARC Processor Hardware Reference
is currently underway. The DDR2 remains in self-refresh mode for at least
t
RAS
and until an internal access (read/write) to DDR2 space occurs.
The self-refresh entry command does automatically disable the
DDR2 memory DLL. Therefore its release command (exit)
requires additional stall cycles until the DLL has re-locked.
Self-refresh exit. When any DDR2 access occurs, the DDR2C asserts
DDR2CKE high which causes the DDR2 to exit from self-refresh mode. The
controller waits to meet the t
XSNR
specification (exit with no read com-
mand) or the t
XSRD
specification (exit with read command). Here is a
significant difference; releasing with a read command requires 200 DDR2
cycles (since the memory DLL needs to re read memory).
System clock during self-refresh mode. Note that the DDR2CLK is not dis-
abled by the controller during self-refresh mode. However, software may
disable the clocks by setting the DIS_DDR2CTL bit in the DDR2CTL0 register.
Programs should ensure that all applicable clock timing specifications are
met before the transfer to DDR2 address space (which causes the control-
ler to exit the self-refresh mode). If a transfer occurs to DDR2 address
space when the DIS_DDR2CTL bit is cleared, an internal bus error is gener-
ated, and the access does not occur externally, leaving the DDR2 in
self-refresh mode.
The following steps are required when using self-refresh mode.
1. Set the DDR2SRF bit to enter self-refresh mode.
2. Poll the
DDR2SRA bit in the DDR2 status register (DDR2STAT) to
determine if the DDR2 has already entered self-refresh mode.
3. Optionally: set the
DIS_DDR2CTL bit to freeze DDR2_CLK.
4. Optionally: clear the
DIS_DDR2CTL bit to re-enable DDR2_CLK.
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