ADSP-214xx SHARC Processor Hardware Reference 21-15
Two Wire Interface Controller
troller is a slave-receiver. If the data associated with the transfer is to be
not acknowledged (NAKed), the
TWINAK bit can be set.
If the TWI controller is to issue a general call as a master-transmitter, the
appropriate address and transfer direction can be set along with loading
transmit FIFO data.
Fast Mode
Fast mode essentially uses the same mechanics as standard mode. It is the
electrical specifications and timing that are different. When fast mode is
enabled using the TWIFAST bit, the following timings are modified to meet
the electrical requirements.
• Serial data rise times before arbitration evaluation (t
r
)
• Stop condition setup time from serial clock to serial data (t
SUSTO
)
• Bus free time between a stop and start condition (t
BUF
)
Interrupts
The following sections provide information on the TWI and interrupt
generation. Table 21-4 provides an overview of TWI interrupts.
If TWI interrupts are routed via the DPI interrupt, programs do
not need to also read the
DPI_IRPTL register for interrupt acknowl-
edge. A write to clear the TWIIRPTL register also clears the
DPI_IRPTL register.
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