Processor Booting
23-14 ADSP-214xx SHARC Processor Hardware Reference
Master Header Information
The transfer is initiated by the transferring the necessary header informa-
tion on the interface (consisting of the read opcode and the starting
address of the block to be transferred, which is usually all zeros). The read
opcode is fixed as 0xC0 (LSBF format) and is 24-bits long. The 8-bits that
are received following the read opcode should be programmed to 0xA5
(see Figure 23-4). If the 8-bits are not programmed to 0xA5 the master
boot transfer is aborted. The transfer continues until 384 x 32-bit words
have been transferred which may correspond to the loader program (just as
in the slave boot mode).
The loader tool of VisualDSP tools automatically includes the SPI
master header information (0xA5).
1. Default state of SPICLK signal high (out of reset).
2. Deasserting the SPI_FLG0_O signal (chip select) to the active low
state and toggling the SPICLK signal.
3. Reading the read command 0x03 (MSBF format to match the
LSBF format) and address 0x00 from the slave device.
Unlike previous SHARC processors, the MOSI pin (DPI pin 02) is
three-stated for SPI master boot mode during reset.
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