ADSP-214xx SHARC Processor Hardware Reference 10-33
Serial Ports
Multichannel mode operates completely independently and each
uses its own SCLK and FS signal programmed using the SRU. The
FS signal synchronizes the channels and restarts each multichannel
sequence. The SPORTx_FS signal initiates the start of the channel 0
data word. The FS period in multichannel is defined as:
FS period = SLEN × number of channels. The frame sync can be
configured in master or slave mode based on the setting of the IMFS
bit and the logic level can be changed using the LMFS bit. The edge
can be changed if bit 2 (FSED) is set in the SPCTLNx register.
Frame Sync Delay (MFD)
The 4-bit MFD field (bits 4–1) in the multichannel control registers
(SPMCTLx) specifies a delay between the frame sync pulse and the first data
bit in multichannel mode. The value of MFD is the number of serial clock
cycles of the delay. Multichannel frame delay allows the processor to work
with different types of telephony interface devices.
A value of zero for MFD causes the frame sync to be concurrent with the
first data bit. The maximum value allowed for MFD is 15. A new frame sync
may occur before data from the last frame has been received, because
blocks of data occur back to back.
Transmit Data Valid Signal
Each SPORT has its own transmit data valid signal (
SPORTx_TDV_0) which
is active during the transmission of an enabled word. Because the serial
port’s receiver signals are three-stated when the time slot is not active, the
SPORTx_TDV_0 signal specifies if the SPORT data is being driven by the
processor.
After the
TXSPxA transmit buffer is loaded, transmission begins and the
SPORTx_TDV signal is asserted.
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