Programming Models
3-130 ADSP-214xx SHARC Processor Hardware Reference
5. DLL in reset starts new locking event. Wait for the DLL to lock to
the new frequency. Note DLL locking time depending on the
CCLK
to DDR2_CLK ratio is:
• 1:2 – 3000 CCLK cycles
• 1:3 – 7500 CCLK cycles
• 1:4 – 10000 CCLK cycles
6. Assign the required external DDR2 banks in the EPCTL register.
7. Wait 8 core cycles for effect latency.
8. Program the refresh rate control register (DDR2RRC).
9. Program the timing parameters in the DDR2CTL1 register.
10.Program all MR and EMR3-1 settings in the DDR2CTL5-3 registers.
11.Enable DDR size (row, column, bank) in the DDR2CTL0 register.
12.Start the power-up sequence with the DDR2PSS bit. Wait for DLL
external bank calibration.
The device now ready for any access.
Frequency Change in Precharge Power-Down Mode
This command allows programs to change the DDR2 clock during run
time. Two different usage cases are relevant: changing the VCO or chang-
ing the core to DDR2 clock. Power-down requires careful software
control since the DRAM is not refreshed. The clock frequency change
must happen in a specific time window (typically t
RAS
max = 8 x t
REFI
or 9
x t
REFI
). If you change the VCO frequency the CLKIN × 4096 < 9 × t
REFI
equation must be met. If it cannnot be met (most cases) the entire clock
To Next Page
Loading...
Need help?
General
