FFT Accelerator
6-24 ADSP-214xx SHARC Processor Hardware Reference
7. Configure a data DMA to write N complex data points from the
accelerator into the output buffer (total of 2N 32-bit words). There
is no need to wait until the DMA in Step 6 completes.
8. Wait until the DMA in Step 7 completes (by interrupt or polling).
The computed FFTs is now in the core’s internal memory and the
accelerator is in reading mode, waiting for next batch of FFTs.
N >= 512, No Repeat
For details on the storage format of the coefficients see “Internal Memory
Storage” on page 6-8.
Configure the FFT Control Register
1. Configure the ACCSEL bits in the PMCTL1 register to select the FFT
accelerator.
2. Factor N = VH, where 16 ≤ V and 16 ≤ H.
3. Set (=1) the FFT_RST bit in the FFTCTL1 register and wait for a min-
imum of 4 CCLK cycles.
4. Program the FFTCTL2 register with
VDIM = V/16
LOG2VDIM = Log2(V)
HDIM = H/16
LOG2HDIM = Log2(H)
NOVER256 = VH/256
FFT_RPT = 0
5. Program the FFTCTL1 register with
FFT_RST = 0
FFT_EN = 1
FFT_START = 1
FFT_DMAEN = 1
FFT_DEBUG = 0
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