ADSP-214xx SHARC Processor Hardware Reference 7-7
Pulse Width Modulation
PCLK clock increments in a PWM period (edge aligned mode) or in a half
PWM period (center aligned mode) in half a PWM period.
Therefore, the PWM switching period, T
s
, can be written as:
T
s
= 2 × PWMTM × t
PCLK
(edge aligned)
T
s
= PWMTM × t
PCLK
(center aligned)
For example, for a 200 MHz
PCLK and a desired PWM center aligned
switching frequency of 10 kHz (T
s
= 100 μs), the correct value to load
into the PWMPERIODx register is:
The largest value that can be written to the 16-bit PWMPERIODx register is
0xFFFF = 65,535 which corresponds to a minimum PWM switching fre-
quency of:
PWMPERIOD values of 0 and 1 are not defined and should not be used
when the PWM outputs or PWM sync is enabled.
Duty Cycles
The two 16-bit read/write duty cycle registers,
PWMA and PWMB, control the
duty cycles of the four PWM output signals on the PWM pins. The
two’s-complement integer value in the
PWMA register controls the duty
cycle of the signals on the
PWM_AH and PWM_AL. The two’s-complement
integer value in the PWMB register controls the duty cycle of the signals on
PWM_BH and PWM_BL pins. The duty cycle registers are programmed in
two’s-complement integer counts of the fundamental time unit,
PCLK, and
define the desired on-time of the high-side PWM signal produced by the
PWMPERIOD
200 10
6
×
210× 10
3
×
------------------------------
10000==
f
PWM()min,
200 10
6
×
2 65535×
--------------------------
1523Hz==
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