Functional Description
7-8 ADSP-214xx SHARC Processor Hardware Reference
two-phase timing unit over half the PWM period. The duty cycle register
range is from:
(–PWPERIOD ÷ 2 – PWMDT) to (+PWPERIOD ÷ 2 + PWMDT)
which, by definition, is scaled such that a value of 0 represents a 50%
PWM duty, cycle. The switching signals produced by the two-phase tim-
ing unit are also adjusted to incorporate the programmed dead time value
in the
PWMDT register. The two-phase timing unit produces active low
signals so that a low level corresponds to a command to turn on the associ-
ated power device.
A typical pair of PWM outputs (in this case for PWM_AH and PWM_AL) from
the timing unit are shown in Figure 7-2 for operation in single update
mode. All illustrated time values indicate the integer value in the associ-
ated register and can be converted to time by simply multiplying by the
fundamental time increment, (PCLK) and comparing this to the two’s-com-
plement counter. Note that the switching patterns are perfectly
symmetrical about the midpoint of the switching period in single update
mode since the same values of the PWMAx, PWMPERIODx, and PWMDTx registers
are used to define the signals in both half cycles of the period.
Further, the programmed duty cycles are adjusted to incorporate the
desired dead time into the resulting pair of PWM signals. As shown in
Figure 7-2, the dead time is incorporated by moving the switching
instants of both PWM signals (PWM_AH and PWM_AL) away from the instant
set by the
PWMAx registers. Both switching edges are moved by an equal
amount (PWMDT x PCLK) to preserve the symmetrical output patterns.
Also shown is the PWM_PHASE bit of the PWMSTAT register that indicates
whether operation is in the first or second half cycle of the PWM period.
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