ADSP-214xx SHARC Processor Hardware Reference 10-51
Serial Ports
The SPORT generates an interrupt when the transmit buffer has a
vacancy or the receive buffer has data. To determine the source of an
interrupt, applications must check the transmit or receive data buffer sta-
tus bits (
DXS_A, DXS_B) in SPCTLx registers and for DMA the corresponding
status bits in the SPMCTLx registers. However note in most cases if both
channels are enabled with the same DMA count, there is no need to check
the status since both channel interrupts are close to each other.
Standard DMA does not function properly in I
2
S/left-justified
mode when two channels (A and B) are enabled with different
DMA count values. In this case, the interrupt is generated for the
least count only. If both the A and B channels of the SPORTs are
used in I
2
S/left-justified mode with DMA enabled, then the DMA
count value should be the same for both channels. This does not
apply to chained DMA.
Error Detection
Similar to previous SHARC processors, the SPORTs can return the status
of data buffer underflow and overflow conditions. Additionally, the
SPORTs can also detect frame syncs that are occurring early, even before
the last transmit or receive completes. To detect these errors, the processor
has an error interrupt (SPERRI vector interrupt) that is shared for all
SPORTs together. It is triggered on a data underflow, data overflow, or
frame sync error in their respective channels. An interrupt is triggered and
programs simply read the
SPERRSTAT register which reduces the processor
overhead needed to do register polling. If the interrupt enable bit SPERRI
is set then the interrupt is raised when the error occurs. Otherwise, the
errors are latched and no interrupt is generated.
As shown in Figure 10-10, the frame sync error (which sets the error bit)
is triggered when an early frame sync occurs during data transmission or
reception or for late frame sync if the period of the frame sync is smaller
then the serial word length (SLEN). However, the current transmit/receive
operation continues without interruption.
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