ADSP-214xx SHARC Processor Hardware Reference 15-17
Serial Peripheral Interface Ports
Variable Frame Delay for Slave
When the processor is configured as an SPI slave, the SPI master must
drive an SPICLK signal that conforms with Figure 15-7. For exact timing
parameters, please refer to the appropriate product data sheet.
As shown in Figure 15-7, the
SPIDS lead time (T1), the SPIDS lag time
(T2), and the sequential transfer delay time (T3) must always be greater
than or equal to one-half the
SPICLK period. The minimum time between
successive word transfers (T4) is two SPICLK periods. This time period is
measured from the last active edge of SPICLK of one word to the first active
edge of SPICLK of the next word. This calculation is independent from the
configuration of the SPI (CPHASE, SPIMS, and so on).
This is shown as:
T4 = 1.5 SPI clock period + T3
and
T3 = 0.5 SPICLK period for STDC = 0.
T3 = STDC × SPICLK period for STDC > 0.
Unlike previous SHARC processors, a variable frame delay is
included to increase SPI timing flexability.
For a master device with CPHASE = 0 or CPHASE = 1 (with AUTODS set to 1 in
the SPCTL register), this means that the slave-select output is inactive
(high) for at least one-half the
SPICLK period. In this case, T1 and T2 are
each always be equal to one-half the
SPICLK period.
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