ADSP-214xx SHARC Processor Hardware Reference A-223
Registers Reference
Pin Assignment Signal Routing
(SRU2_PINx, Group B)
Group B connections, shown in Figure A-124 through Figure A-126 and
Table A-119, are used to route output signals to the 14 DPI pins.
For the ADSP-2147x and ADSP-2148x processors, the outputs of
PWM units 3–1 can be routed to the DPI pins. See locations 0x23
– 0x2E in Table A-119.
Figure A-124. SRU2_PIN0 Register
Figure A-125. SRU2_PIN1 Register
DPI_PB05_I (29–24)
DPI pin buffer 5 Input
DPI_PB03_I (17–12) con’t
DPI Pin Buffer 3 Input
DPI_PB04_I (23–18)
DPI Pin Buffer 4 Input
DPI_PB03_I (17–12)
DPI_PB02_I (11–6)
DPI Pin Buffer2 Input
DPI_PB01_I (5–0)
DPI Pin Buffer 1 Input
DPI Pin Buffer 3 Input
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
DPI_PB10_I (29–24)
DPI Pin Buffer 10 Input
DPI_PB08_I (17–12) con’t
DPI Pin Buffer 8 Input
DPI_PB09_I (23–18)
DPI Pin Buffer 9 Input
DPI_PB08_I (17–12)
DPI_PB07_I (11–6)
DPI Pin Buffer 7 Input
DPI_PB06_I (5–0)
DPI Pin Buffer 6 Input
DPI Pin Buffer 8 Input
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
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