Clocking
2-22 ADSP-214xx SHARC Processor Hardware Reference
Clocking
The fundamental timing clock of the IOP is peripheral clock (PCLK). All
DMA data transfers over the IO0 or IO1 buses are clocked at PCLK speed.
Functional Description
The following several sections provide detail on the function of the I/O
processor.
Automated Data Transfer
Because the IOP registers are memory-mapped, the processors have access
to program DMA operations. A program sets up a DMA channel by writ-
ing the transfer’s parameters to the DMA parameter registers. After the
index, modify, and count registers (among others) are loaded with a start-
ing source or destination address, an address modifier, and a word count,
the processor is ready to start the DMA.
The peripherals each have a DMA enable bit in their channel control reg-
isters. Setting this bit for a DMA channel with configured DMA
parameters starts the DMA on that channel. If the parameters configure
the channel to receive, the I/O processor transfers data words received at
the buffer to the destination in internal memory. If the parameters config-
ure the channel to transmit, the I/O processor transfers a word
automatically from the source memory to the channel’s buffer register.
These transfers continue until the I/O processor transfers the selected
number of words as determined by the count parameter. DMA through
the IDP ports occurs in receive mode (into internal memory) only.
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