Overview
A-2 ADSP-214xx SHARC Processor Hardware Reference
and registers definitions. An #include file is provided with VisualDSP++
tools and can be found in the
VisualDSP/214xx/include directory.
Overview
The I/O processor’s registers are accessible as part of the processor’s mem-
ory map. “Register Listing” on page A-273 lists the I/O processor’s
memory-mapped registers and provides a brief description of each register.
Since the I/O processor registers are memory-mapped, the processor’s
architecture does not allow programs to directly transfer data between
these registers and other memory locations, except as part of a DMA oper-
ation. To read or write I/O processor registers, programs must use the
processor core registers.
The register names for I/O processor registers are not part of the proces-
sor’s assembly syntax. To ease access to these registers, programs should
use the header file containing the registers’ symbolic names and addresses.
Register Diagram Conventions
The register drawings in this appendix provide “at-a-glance” information
about specific registers. They are designed to give experienced users basic
information about a register and its bit settings. When using these regis-
ters, the following should be noted.
• In cases where there are multiple registers that have the same bits
(such as serial ports), one register drawing is shown and the names
and addresses of the other registers are simply listed. Also, depend-
ing on peripheral (such as ASRC), if two different ASRC ports are
programmed in the same register, one peripheral is defined with a x
the other with a y index.
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