ADSP-214xx SHARC Processor Hardware Reference 6-55
FFT/FIR/IIR Hardware Modules
IIR Accelerator
The ADSP-214xx processors have an IIR filter accelerator implemented in
hardware, that reduces the processing load on the core, freeing it up for
other tasks.
Features
The accelerator supports a maximum of 24 channels. There is support for
up to 12 cascaded bi-quads per channel. This means that the accelerator
locally stores all the biquad coefficients of 24 channels. Window size can
be configured from 1 (sample based) to 1024.
• IIR supports IEEE floating point format 32/40-bit
• Sample based or window based processing
• Up to 12 cascaded biquads per channel
• Up to 24 filter channels available
Register Overview
The following sections provide information on the IIR accelerator control
and status registers.
Power Management Control Register (PMCTL1). Used for IIR accelera-
tor selection. Controls the clock power down to the module if not
required.
IIR Global Control (IIRCTLx). Configures the global parameters for the
accelerator. These include number of channels, channel auto iterate,
DMA enable, and accelerator enable.
The
IIRCTL2 register is used to configure the channel specific parameters.
These include number of biquads and window size.
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