FIR Accelerator
6-54 ADSP-214xx SHARC Processor Hardware Reference
2. Create six TCBs in internal memory with each channel’s chain
pointer (CP) entry pointing to the next channel’s and the sixth
channel’s CP entry pointing back to the first’s in a circular fashion.
3. Configure the
FIRCTL2 register for the first four channels’ TCBs to
256 TAPs and a window size of 128, and the next two channels for
1024 TAPs and a window size of 128, respectively.
4. Configure the index, modifier, length entries in the TCBs to point
to the corresponding channel’s data buffer, coefficient buffer, and
output data buffer. The location of the first channel’s TCB is writ-
ten to the CPFIR register. The FIRCTL1 register is then programmed
with an FIR_CH value that corresponds to six channels.
a. The accelerator iterates through six channels once and then
waits for core intervention, (the FIR_CAI bit is not set, the
DMA is enabled, and the FIR_EN bit is set).
b. The accelerator then loads the first channel’s TCB then
loads the coefficient and data and processes one window.
c. After saving the index values to memory the accelerator
moves to the next channel.
d. After all six channels are complete the accelerator halts and
waits for core intervention.
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