ADSP-214xx SHARC Processor Hardware Reference 11-25
Input Data Port
Debug Features
The following sections describe the features available for debugging the
IDP.
Status register Debug
The core may also write to the FIFO. When it does, the audio data word is
pushed into the input side of the FIFO (as if it had come from the SRU
on the channel encoded in the three LSBs). This can be useful for verify-
ing the operation of the FIFO, the DMA channels, and the status portions
of the IDP. The IDP_STAT1 register returns the current state of the
read/write index pointers from FIFO.
Buffer Hang Disable
The IDP_BHD bit in IDP_CTL0 is used for buffer hang disable control. When
there is no data in the FIFO, reading the IDP_FIFO register causes the core
to hang. This condition continues until the FIFO contains valid data. Set-
ting the IDP_BHD bit (= 1) prevents the core from hanging on reads from
an empty IDP_FIFO register. Clearing this bit (= 0) causes the core to hang
under the conditions described previously.
If the IDP_BHD bit (bit 4 in the IDP_CTL0 register) is not set, attempts to
read more data than is available in the FIFO results in a core hang.
Shadow Registers
The DAI interrupt controller contains shadow registers to simplify debug
techniques since these register are not updated. A read of the
DAI_IMASK_x_SH register provides the same data as a read of the
DAI_IMASK_x register. Reading these DAI shadow registers
(DAI_IMASK_x_SH) does not destroy the contents of the DAI_IMASK_x
registers.
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