Functional Description
7-12 ADSP-214xx SHARC Processor Hardware Reference
since for the general case in double- update mode, the switching period is
given by:
Again, the values of T
AH
and T
AL
are constrained to lie between zero and
T
S
. Similar PWM signals to those illustrated in Figure 7-2 and Figure 7-3
can be produced on the BH and BL outputs by programming the PWMBx
registers in a manner identical to that described for the PWMAx registers.
Dead Time
The second important parameter that must be set up in the initial config-
uration of the PWM block is the switching dead time. This is a short delay
time introduced between turning off one PWM signal (say AH) and turn-
ing on the complementary signal, AL. This short time delay is introduced
to permit the power switch being turned off (AH in this case) to completely
recover its blocking capability before the complementary switch is turned
on. This time delay prevents a potentially destructive short-circuit condi-
tion from developing across the DC link capacitor of a typical voltage
source inverter.
The 10-bit, read/write
PWMDT3–0 registers control the dead time. The dead
time, T
d
, is related to the value in the PWMDTx registers by:
Therefore, a PWMDT value of 0x00A (= 10), introduces a 200 ns delay
between when the PWM signal (for example AH) is turned off and its com-
plementary signal (
AL) is turned on. The amount of the dead time can
d
AH
T
AH
T
H
------------
1
2
---
PWMCHA
1
PWMCHA
2
PWMDT
1
PWMDT
2
––+()
PWMPERIOD
1
PWMPERIOD
2
+()
------------------------------------------------------------------------------------------------------------------------------------------
+==
T
S
PWMPERIOD
1
PWMPERIOD
2
+()t
PCLK
×=
To Next Page
Loading...
Need help?
General
