ADSP-214xx SHARC Processor Hardware Reference A-211
Registers Reference
Status Register (RTC_STAT)
This register, shown in Figure A-111, The RTC Status register contains
the RTC event flags and RTC interrupt status. These bits are sticky. Once
set by the event, each bit remains set until cleared by a software read of
this register. These sticky bits are independent of the interrupt enable bits
in RTC_CTL register. Values are cleared by reading RTC_STAT register,
except for the WR_PEND, ALRM_PEND and DAYALRM_PEND bits. Writes to any
bit of this register has no effect. This register is cleared at reset.
4DAY_INTEN Days Interrupt Enable.
0 = Days interrupt disabled
1 = Days interrupt enabled
5ALRM_INTEN Alarm Interrupt Enable.
0 = Alarm interrupt disabled
1 = Alarm interrupt enabled
6 DAYALRM_INTEN Day Alarm Interrupt Enable.
0 = Day alarm interrupt disabled
1 = Day alarm interrupt enabled
7 SW_INTEN Stopwatch Interrupt Enable.
0 = Stopwatch interrupt disabled
1 = Stopwatch interrupt enabled
81HzCKFAIL_INTENRTC 1Hz Clock Fail Interrupt Enable. Indicates that the
oscillator failed to start.
0 = RTC 1Hz clock fail interrupt disabled
1 = RTC 1Hz clock fail interrupt enabled
9 EMU_INTDIS Disables/Enables RTC Interrupts in Emulation Mode.
0 = RTC interrupts enabled (if the individual interrupt
enable bit is set) in emulation mode
1 = RTC interrupts disabled in emulation mode
Table A-113. RTC_CTL Register Bit Descriptions (RW) (Cont’d)
Bit Name Description
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