ADSP-214xx SHARC Processor Hardware Reference I-15
Index
L
LAFS (late transmit frame sync select) bit,
10-24, 10-27, A-155, A-159
latchup, 23-33
latency
input synchronization, 23-30
in SPORT registers, 10-55
link ports, 4-15
left-justified mode, 10-28, C-5
SRC, 12-9, A-186
SRC timing, 12-9
left-justified sample pair mode
control bits, 10-29
Tx/Rx on FS rising edge, 10-24
length registers, DMA, 2-8
life counter, 18-1
Link buffer DMA chaining enable
(LxCHEN) bit, A-64
Link buffer DMA enable (LxDEN) bit,
A-64
Link buffer enable (LxEN) bit, A-64
Link buffer transmit/receive (LxTRAN)
bit, A-64
link port, 4-5
boot bit settings, 23-22
booting, 23-21
DMA, 4-24
handshake timing, 4-6
initialization for boot, 23-22
interrupts, 4-16 to 4-21
token passing, 4-11
link port bits
DMA channel count mask
(DMACH_IRPT_MSK), A-65
external transfer done mask
(EXTTXFR_DONE_MSK), A-65
receive request mask (LRRQ_MSK),
A-65
transmit request mask (LTRQ_MSK),
A-64
Link port control (LCTL) register, A-64
Link port receive request status (LxRRQ)
bits, A-66
link ports
chained DMA, 2-15
transmit status (LTRQ) bit, A-66
Link port transmit request status (LxTRQ)
bits, A-66
LIRPTL (interrupt) registers, 15-26
logical vs. physical address, 3-90
loopback mode
timers, 16-19, 18-12, 19-7
loopback mode, SPI, 15-28
loop-back test, MLB, 8-
16
low active transmit frame sync (LFS, LTFS
and LTDV) bits, A-196
LRFS (SPORT logic level) bit, 10-20
LSBF (least significant bit first) bit, A-153
M
MAC status (IIRMACSTAT) register, 6-56
making connections via the signal routing
unit, 9-20
manual
contents, lxii
conventions, lxx
new in this edition, -xv
manual revisions, lxv
mapping addresses, DDR2, 3-65
maskable interrupts, SPI, 15-26
mask bits, interrupt, 2-45
masking interrupts, link port, 4-20
master input slave output (MISOx) pins,
15-8, 15-14
slave output, 15-14
master mode enable, 10-25, 10-30
master mode operation, SPI, 15-30
master out slave in (MOSIx) pin, 15-8,
15-14
master-slave interconnections, 15-3
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