ADSP-214xx SHARC Processor Hardware Reference A-79
Registers Reference
Debug Registers (FFTDADDR, FFTDDATA)
Bits 31–0 is the
FFT_DDATA register correspond to the data to be read or
written. When a data write is performed first this register is loaded with
data which needs to be written, then the FFT_DADDRESS register is loaded
with the write address of the location. Note that these registers should be
written/read only in debug mode. In Table A-46, A is a meaningful
address bit.
FIR Accelerator Registers
The following sections describe the registers used to program and debug
the FIR accelerator.
Global Control Register (FIRCTL1)
The
FIRCTL1 register, shown in Figure A-35 and described in Table A-47,
is used to configure the global parameters for the accelerator. These
include the number of channels, channel auto iterate, DMA enable, and
accelerator enable.
Table A-46. DADDRESS Register Bit Descriptions (RW)
Bits Name Description
12–0 ADDRESS Address Bit. Access to local memory requires debug mode. The
MSB bits of the address decode the memory location.
000AAAAAAAAAA = read data memory (2^10)
100AAAAAAAAAA = write data memory (2^10)
010xAAAAAAAAA = read coefficient memory (2^9)
110xAAAAAAAAA = write coefficient memory (2^9)
A = valid address bits
31–13 Reserved
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