Analog Devices SHARC ADSP-214 Series - Large FFT N>=256

ADSP-214xx SHARC Processor Hardware Reference 6-9
FFT/FIR/IIR Hardware Modules
Large FFT N>=256
To run a large FFT 7 buffers are required:
• Input Buffer [2 × N] (packed data)
• Special Buffer [2 × N] (intermediate buffer used in step 1 for verti-
cal FFT and in step 2 for special product = Product of vertical
buffer with special twiddles)
• Output Buffer [2 × N] (packed data)
• Vertical Coeff Buffer [2 × V]
• Horizontal Coeff Buffer [2 × H]
• Special Coeff Buffer [4 × N]
Twiddles
For N>256, the FFT accelerator follows the ‘Divide and Conquer’
approach. Therefore, three types of coefficient buffers are required:]
Coefficient buffer for V point FFT
Re(CF[0]), Im(CF[0]), -Im(CF[0]), Re(CF[0]),
Re(CF[1]), Im(CF[1]), -Im(CF[1]), Re(CF[1]),
..........
Re(CF[V/2-1]), Im(CF[V/2-1]), -Im(CF[V/2-1]), Re(CF[V/2-1])
(4xV/2 = 2V words)
Coefficient buffer for H point FFT
Re(CF[0]), Im(CF[0]), -Im(CF[0]), Re(CF[0]),
Re(CF[1]), Im(CF[1]), -Im(CF[1]), Re(CF[1]),
..........
Re(CF[H/2-1]), Im(CF[H/2-1]), -Im(CF[H/2-1]), Re(CF[H/2-1])
(4xH/2 = 2H words)
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