ADSP-214xx SHARC Processor Hardware Reference 3-11
External Port
Features
The AMI has the following features and capabilities.
• User defined combinations of programmable wait states
• External hardware acknowledge signals
• Data packing support for 8 and 16 bits (ADSP-2147x and
ADSP-2148x)
• External instruction fetch from 8 and 16 bits
• Both the processor core and the I/O processor have access to exter-
nal memory using the AMI.
• Support a glueless interface with any of the standard SRAMs.
• Bank 0 can accommodate up to 6.2M words, and banks 1, 2, and 3
can accommodate up to 8M words each (ADSP-2147x and
ADSP-2148x)
• Bank 0 can accommodate up to 2M words, and banks 1, 2, and 3
can accommodate up to 4M words each (ADSP-2146x)
Functional Description
The following sections provide a functional overview of the asynchronous
memory interface.
The AMI communicates with SRAM, FLASH and any other memory
device that conforms to its protocol. It provides a DMA interface between
internal memory and external memory, performs instruction (48-bit) fetch
from external memory, and directs core access to external memory loca-
tions. The AMI on the ADSP-2147x and ADSP-2148x supports 8- and
16-bit data access to external memory.
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