Clocking
20-4 ADSP-214xx SHARC Processor Hardware Reference
Transmit Buffer Control Register (UARTxTXCTL). Controls core or
DMA operation.
Receive Buffer Control Register (UARTxRXCTL). Controls core or
DMA operation.
Interrupt Enable Control Register (UARTxIER). Enables interrupt
requests from system handling.
Line Status Register (UARTxLSR). Returns status of controls format of
the data character frames as overrun or framing errors and break
interrupts.
Transmit Status Register (UARTxTXSTAT). Returns status of core or
DMA operation.
Receive Status Register (UARTxRXSTAT). Returns status of core or
DMA operation.
Interrupt Identification Status Register (UARTxIIR). Provides status of
all interrupts and combines them into one channel.
Clocking
The fundamental timing clock of the UART module is peripheral
clock/16 (
PCLK/16).
The bit rate is characterized by the peripheral clock (
PCLK) and the 16-bit
divisor. The divisor is split into the UART divisor latch low byte register
(
UARTDLL) and the UART divisor latch high byte register (UARTDLH). These
registers form a 16-bit divisor. The baud clock is divided by 16 so that:
• Divisor = 1 when
UARTDLL = 1 UARTDLH = 0
• Divisor = 65,535 when
UARTDLL = UARTDLH = FF
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