Power-Up Sequence
22-8 ADSP-214xx SHARC Processor Hardware Reference
Normal Mode
The normal mode is the regular mode and is effective if the PLLBP bit is
cleared. In normal mode the PLL has locked and multiplies CLKIN to the
desired VCO clock. The output clock generator post divides and provides
the clock tree to the I/O.
The change of PLL frequency can happen at any time (for example
after power-up or during operation).
Clocking Golden Rules
The five rules below should be followed to ensure proper processor
operation.
1. After power-up the CLK_CFG pins should not exceed the maximum
core speed.
2. Software should guarantee minimum/maximum CCLK speed.
3. Software should guarantee maximum VCO clock speed.
4. Bypass requires 4096 CLKIN cycles.
5. Post divider changes require 14 CCLK cycles.
Power-Up Sequence
The proper power-up sequence is critical to correct processor operation as
described in the following sections.
To Next Page
Loading...
