ADSP-214xx SHARC Processor Hardware Reference 11-13
Input Data Port
Packing by 4
Packing by 4 moves data in four cycles. Each input word can be up to
eight bits wide.
• On clock edge 1, bits 19–12 are moved to bits 7–0
• On clock edge 2, bits 19–12 are moved to bits 15–8
• On clock edge 3, bits 19–12 are moved to bits 23–16
• On clock edge 4, bits 19–12 are moved to bits 31–24
This mode sends one packed 32-bit word to FIFO for every four input
clock cycles—the DMA transfer rate is one-quarter the PDAP input clock
rate.
Figure 11-5. PDAP Hold Input (Packing by 4)
PDAP_CLK_I
PDAP DATA
PDAP_HOLD_I
B0 B1 B2
B3
B0
B0 B1 B2
B3
PDAP_STROBE_O
PDAP_CLK_I
PDAP DATA
PDAP_HOLD_I
PDAP_STROBE_O
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