ADSP-214xx SHARC Processor Hardware Reference 14-19
Precision Clock Generator
For more information on core clock setting, see “ADSP-2146x Power
Management Registers” on page A-6 and “ADSP-2147x/ADSP-2148x
Power Management Registers” on page A-12.
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
PCG Effect Latency
After the PCG registers are configured the effect latency is shown below.
The latency to start the CLKOUT depends on the divisor value and input
source as described below.
Input clock through PCLK
• If divisor value is 0 or 1 (bypassed) the latency is 1 PCLK cycle
• For other divisor values the latency is 3
PCLK cycles
Input clock through
CLKIN
• If divisor is 0 or 1 (bypassed) the latency can vary from 0 to 1 oscil-
lator period. This is because clock generation starts with the
immediate positive edge of the
CLKIN.
• For other divisor values the latency can vary between 2 to 3 oscilla-
tor periods. This is because clock generation starts with the third
positive edge of CLKIN.
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