ADSP-214xx SHARC Processor Hardware Reference 12-15
Asynchronous Sample Rate Converter
Decimation Rate
The RAM in the FIFO is 512 words deep for both left and right channels.
An offset to the write address provided by the f
S
_IN counter is added to
prevent the RAM read pointer from ever overlapping the write address.
The offset is fixed by the group delay signal. A small offset, 16, is added to
the write address pointer.
Increasing the offset of the write address pointer is useful for applications
when small changes in the sample rate ratio between f
S
_IN and f
S
_OUT
are expected. The maximum decimation rate can be calculated from the
RAM word depth and GRPDLYS as (512 – 16)/64 taps = 7.75:1.
Muting Modes
The mute feature of the SRC can be controlled automatically in hardware
using the MUTE_IN signal by connecting it to the MUTE_OUT signal. Auto-
matic muting can be disabled by setting (=1) the SRCx_MUTE_EN bits in the
SRCMUTE register.
Note that by default, the SRCMUTE register connects the MUTE_IN sig-
nal to the
MUTE_OUT signal, but not vice versa.
Soft Mute
When the SRCx_SOFTMUTE bit in the SRCCTL register is set, the MUTE_IN sig-
nal is asserted, and the SRC performs a soft mute by linearly decreasing
the input data to the SRC FIFO to zero, (–144 dB) attenuation as
described for automatic hardware muting.
GDS
16
SRCx_FS_IP
-------------------------------
32
SRCx_FS_IP
-------------------------------
SRCx_FS_IP
SRCx_FS_OP
---------------------------------
× onds for SRCx_FS_OP SRCx_FS_IP≤()sec+=
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