ADSP-214xx SHARC Processor Hardware Reference 6-17
FFT/FIR/IIR Hardware Modules
One transfer control block (TCB) needs to be configured for each chan-
nel. The TCB contains:
• A control register value to configure the FFT parameters for each
channel.
• DMA parameter register values for input data.
• DMA parameter register values for twiddles load.
• DMA parameter register values for output data.
Intermediate results for large FFT are stored in the internal
memory.
The circular access type is used for large FFTs to process the entire
FFT (VxH) matrix.
Interrupts
The FFT accelerator has two interrupts that are programmable through
the programmable interrupt priority control register (see Appendix B,
Figure 6-2. Circular Buffer Addressing
20
19
5
4
2
3
1
.
.
.
Index Register
Base Register
Buffer Length
Register
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