Overview
C-2 ADSP-214xx SHARC Processor Hardware Reference
Overview
The following protocols are available in the SHARC processor and are
briefly described in this appendix. For complete information on the indus-
try standard protocols, see the specification listings in each section.
• Standard Serial Mode
• Left-justified Mode (Sony format)
•I
2
S Mode (Sony/Philips format)
• Time Division Multiplex (TDM) Mode
• MOST Mode
• Right-justified Mode
• S/PDIF (consumer mode)
• EBU/AES3 (professional mode)
Standard Serial Mode
Most processors allow word lengths of 4 to 32 bits to be transmitted or
received through their serial ports. For convenience, most AFE (analog
front-end) devices operate with 16-bit word lengths for both data and sta-
tus transfer between the AFE and processor. The serial ports (SPORTs) of
most DSPs are designed for full-duplex operation. They differ from the
typical serial interface of micro controllers in that they use a frame sync
pulse to indicate the start of the data frame. In the case of full duplex asyn-
chronous transfers, two separate FS pulses are used for transmit and
receive. The typical micro controller serial interfaces use the serial clock
(SCLK) as an indicator of serial data, meaning that the SCLK is only active
when data is valid. The DSP serial interface can operate with a continuous
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