ADSP-214xx SHARC Processor Hardware Reference 3-85
External Port
Whenever the
AMITX buffer is empty, the DMA controller or a direct
access from the processor core can write new data into the AMI. If the reg-
ister is full, further writes from the core (or DMA controller) are stalled.
For core and DMA access, the received data is also unpacked,
depending on the setting of the PKDIS bit. The order of unpacking
is dependent on the MSWF bit in AMICTLx registers.
DMA Buffer
The external port supports two DMA channels, each populated with a
data buffer (DFEP1–0). Each data buffer is 6 locations deep and its status
can be read in the DMACx register. Note the DMA channels are valid for
AMI, SDRAM or DDR2 transfers. For more information, see “External
Port DMA” on page 3-100.
Core Access
For core-driven external port transfers, the instruction needs to read or
write from a valid external port address.
External Port Dual Data Fetch
The dual data fetch instruction (Type 1) allows the processor to access
external data from both DAGs. In such an instruction, the accesses are
executed sequentially (not simultaneously as in internal memory). For
example:
r4=r2+r3, r2=dm(i6,m6), r3=pm(i10,m10);
The DAG1 access (operand r2) is executed first followed by the second
DAG2 access (operand r3).
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