ADSP-214xx SHARC Processor Hardware Reference 4-23
Link Ports—ADSP-2146x
Changing the Link Port Clock
The following programming sequence may be used to change the
core-to-link port clock ratio only. Note that this procedure changes only
the PLL output divider. Therefore programs do not need to wait 4096
CLKIN cycles (required only if the PLL multiplier or the INDIV bit is
modified).
1. Disable the link ports. Note that the peripherals cannot be enabled
when changing clock ratio.
2. Select the PLL divider by setting the PLLDx bits (bits 6–7 in the
PMCTL register).
3. Select the link port clock divider (CCLK to LPCLK ratio) by setting
the LPCKRx bits (bits 21 and 22 in the PMCTL register).
4. Enable the new divisors by setting the DIVEN bit (bit 9 in the PMCTL
register).
5. Wait 15 CCLK cycles. During this time, programs must not execute
any valid instructions. The LPCLK change does not happen
on-the-fly. This means that when a clock ratio change is registered,
the current clock cycle may get truncated before the change and the
new clock cycle ratio start.
6. Enable link ports.
For more information on link port clocking and programming the PLL,
see “Phase-Locked Loop (PLL)” on page 22-2.
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