Register Overview
17-4 ADSP-214xx SHARC Processor Hardware Reference
The shift register input pins (
SR_CLK_I, SR_LAT_I, SR_SDI_I) are routed by
default to the external shift register pins (SR_CLK, SR_LAT, SR_SDI).
Register Overview
The processor contains registers that are used to control the shift register.
• Control Register (SHREGCTL). Used to clear/reset the shift reg-
ister in software, select the data source for the SR_SDO_O pin out of
the 18 bits of the register, and to enable parallel data output. Com-
plete bit description can be found at TBD.
• Clock Routing Register (SRU_CLK_SHREG). Configures the
clock source. For more information, see “Clock Routing Register
(SRU_CLK_SHREG)” on page A-145.
• Data Routing Register (SRU_DAT_SHREG). Configures the data
source. For more information, see “Data Routing Register
(SRU_DAT_SHREG)” on page A-147.
Clocking
The shift register requires two clock inputs: SR_SCLK_I for the serial shift
register and
SR_LAT_I for the latch. The source of these clocks is selectable
out of many sources such as the SPORTs, PCGA/B, DAI pin buffers 8–1,
or dedicated SR_SCLK and SR_LAT input pins. The data is shifted on the ris-
ing edge of the SR_SCLK_I and the data from the shift register is transferred
to the latch on rising edge of the SR_LAT_I. If both clocks are connected
together, the shift register is always one clock pulse ahead of the latch.
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