ADSP-214xx SHARC Processor Hardware Reference 5-5
Memory-to-Memory Port DMA
MTM Throughput
Data throughput for internal to internal transfers is 12 PCLK cycles for
64-bit data.
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
MTM Effect Latency
After the MTM register is configured the effect latency is 1.5 PCLK cycles
minimum and 2 PCLK cycles maximum.
Programming Model
This data transfer can be set up using the following procedure.
1. Program the DMA registers for both channels.
2. Set (=1) the MTMFLUSH bit (bit 1) in the MTMCTL register to flush the
FIFO and reset the read/write pointers.
3. Set (=1) the MTMEN bit in the MTMCTL register.
A two-deep, 32-bit FIFO regulates the data transfer through the
DMA channels.
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