IIR Accelerator
6-66 ADSP-214xx SHARC Processor Hardware Reference
The 40-bit wide debug mode write data register is organized as:
• The
IIRDBGWRDATA_L register holds the lower 32 bits and
• The IIRDBGWRDATA_H register holds the upper 8 bits
A read from the IIRDBGRDDATA_L register followed by a read from the
IIRDBGRDDATA_H register returns the content of the 40-bit memory loca-
tion pointed to by the address register. Data can be written into any
memory location using the IIRDBGWRDATA_L register followed by the
IIRDBGWRDATA_H register.
If the address auto increment bit (IIR_ADRINC) is set, the address register
auto increments on IIRDBGWRDATA_H/L writes and IIRDBGRDDATA_H/L reads.
During auto increment, the IIR_DBGADDR register cannot cross the data
memory/coefficient memory boundary. The address boundary for data
memory is 1024 locations and for coefficient memory 2048 locations
Single Step Mode
Programs can single step through the MAC operations and observe the
memory contents after each step. The IIR_DBGMODE/IIR_HLD and IIR_RUN
bits control the IIR MAC units.
Emulation Considerations
In IIR debug mode, the DMA operations are not observable.
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
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